1. Technical Field
This invention relates to apparatus and methods for communicating data, and more specifically communicating data over a plurality of channels, such as a cable having a plurality of conductors (for example, four twisted pairs of wires), and for encoding and/or decoding data in connection with such communications.
2. Background Art
FIG. 1 illustrates the prior art transition minimized differential signaling (TMDS) physical layer that was developed by Silicon Image Inc. as a member of the Digital Display Working Group and is used in both the well-known Digital Visual Interface (DVI) and High Definition Multimedia Interface (HMDI).
TMDS is a physical layer technology for transmitting high-speed serial data in a simplex mode from one transmitter to one receiver. A useful description of this TMDS interface is included in the background section of Hwang (U.S. Pat. No. 7,359,437). The TMDS transmitter incorporates a coding algorithm designed to minimize electromagnetic interference (EMI) over copper cables. The algorithm is a form of eight-bit binary to ten-bit binary (8B:10B) coding, similar to that described in Franaszek (U.S. Pat. No. 4,486,739) but using a different code-set that differs from the IBM originated form. Hwang describes yet another form of eight-bit binary to ten-bit binary (8B:10B) coding that may be more effective than the TMDS coding algorithm at reducing inter-symbol interference. Each TMDS ten-bit word can represent either an eight-bit data value, typically representing video pixel data, or alternatively a two-bit control value, typically used for horizontal and vertical sync during screen blanking. Such a TMDS coding algorithm can therefore be described as an eight-symbol, alternatively two-symbol, binary (base-two) to ten-symbol binary (base-two) coding algorithm and is represented herein in short hand form as ‘8/2B:10B’.
In the TMDS coding scheme, four hundred sixty (460) combinations, out of the possible one thousand twenty four (1024) combinations, for a 10-bit binary word, are used for representing an 8-bit data value. Some of the two hundred fifty six (256) possible values, of each 8-bit binary word, are encoded using a single variant and other values have two encoded variants. Four combinations, of the 10-bit binary output word, are used for representing a 2-bit control word used for TMDS control signals, such as horizontal and vertical sync video signals.
FIG. 1 depicts a typical TMDS interface configured to transmit red-green-blue (RGB) video data. TMDS uses four twisted wire pairs (120, 121, 122, and 123) to transmit a clock channel 130 and three data channels (131, 132, and 133). Red video data 131 is transmitted as a serial stream of ten, as described above, 2-level (binary) symbols per pixel into a first twisted pair 121 of wires at a rate of between 250 MHz and 3.4 GHz. Green video data 132 is transmitted as a serial stream of ten 2-level (binary) symbols per pixel into a second twisted pair 122 of wires at a rate of between 250 MHz and 3.4 GHz. Blue video data 133 is transmitted as a serial stream of ten 2-level (binary) symbols per pixel into a third twisted pair 123 of wires at a rate of between 250 MHz and 3.4 GHz. A pixel clock 100 transmits clock data 130 consisting of one 2-level (binary) symbol per pixel into a fourth twisted pair 120 of wires at a rate of between 25 MHz and 340 MHz, or one-tenth the symbol rate of the data channels.
TMDS uses DC-coupled current mode logic (CML), terminated to 3.3 volts and DC balanced by the encoding algorithm. Each TMDS data channel includes an eight-symbol, alternatively two-symbol, binary (base-two) to ten-symbol binary (8/2/B:10B) encoder (11R, 11G, and 11B), a twisted wire pair (121, 122, and 123), and a ten-symbol binary to eight-symbol, alternatively two-symbol, binary decoder (17R, 17G, and 17B). The clock channel 130 is used for inter-channel alignment 101, such as between the three data channels (131, 132, and 133), at the receiving side of the interface. Typical TMDS data channels (131, 132, and 133) will also include pre-emphasis stages (12R, 12G, and 12B) and equalization stages (16R, 16G, and 16B).
In a different area of the prior art, communication systems have been developed which use more than two voltage levels to represent digital data. For example, a four-level pulse amplitude modulated system (PAM-4) will encodes two binary bits at a time and map the resulting signal amplitude to one of four possible voltage levels, such as −3 volts, −1 volt, 1 volt, and 3 volts. Demodulation is performed by detecting the amplitude level of the carrier at every symbol period. Each of these prior art systems transmits data in two-directions (full-duplex) and derives a clock signal from its data channels, rather than having a dedicated clock channel.
Phanse (U.S. Pat. No. 6,975,674) describes a PAM-5 (e.g. five voltage levels per symbol) interface that is suitable for transmitting 125 mega-symbols per second (125 MHz) per twisted wire pair on a four-pair Cat 5e cable resulting in an aggregate transmission of 500 mega-symbols per second (500 MHz) per direction in a full-duplex transmission configuration. According to Phanse, this allows for a (binary) data rate of one gigabit per second (1 Gbps). Phanse is not applicable as a replacement for TMDS because it does not have enough bandwidth for the highest video rates and because it relies on recovering the clock from the data stream, has a significant DC residual correction required, and requires echo cancellation circuitry due to the duplex nature of its anticipated communication path.
Deliot (U.S. Pat. No. 6,052,390) describes a PAM-9 (e.g. nine voltage levels per symbol) interface and is instructive in the need to manage DC residual when using multi-level signals in a transformer coupled system as well as the effect of overall energy from a multi-level symbol group in terms of resultant electromagnetic interference (EMI). However, Deloit requires that delimiters be inserted between multi-level symbol groups which introduces a significant processing overhead that is not desirable when associated with high speed video data transfer.
There continues to be a long-felt need to extend the cabling length and/or bandwidth available for high-definition media interface (HDMI) television signals which is unanswered by the prior art.